1. Technical Field
The present invention relates generally to methods of forming a semiconductor device and device structures formed thereby and, more particularly, to methods of fabricating semiconductor devices having a barrier metal layer and device structures formed thereby.
2. Discussion of Related Art
Generally, a semiconductor device is fabricated by forming various circuit structures through processes of depositing thin films to perform many functions and patterning them. The fabrication processes of a semiconductor device typically include a deposition process of forming layers on a semiconductor substrate; an etch process, such as photolithography, in which a photoresist layer is formed on the layers formed through the deposition process, the photoresist layer is exposed using a mask, and the layers are patterned using the patterned photoresist layer as an etch mask; a chemical mechanical polishing (CMP) process of depositing an interlayer insulating layer on the semiconductor substrate and polishing the top surface of the semiconductor substrate to remove a step height difference; and the like.
Recently, with a rapid development of telecommunication systems and a rapidly spreading popularity of data storage mediums, such as computers, semiconductor devices have also had significant developments. It may be desired that semiconductor devices be driven at a high speed, and have a large amount of storage capability. Therefore, the integration of semiconductor devices has gradually increased. With the increase of the integration of the semiconductor devices, the line width of a gate electrode and a contact size are also reduced, which may cause problems, such as increasing resistance of the active region and the gate region, and contact resistance. Therefore, recently in the fabrication of highly integrated semiconductor devices, a barrier metal is formed on the active region and the gate region to reduce resistances of the active region and the gate region and reduce a contact resistance so as to increase current driving capability.
FIG. 1 illustrates a conventional DRAM structure in which barrier metal is used in an active region and a gate region. Referring to FIG. 1, a p-type (or n-type) semiconductor substrate 10 is provided in which an active region and a field region are divided by a device isolation layer 12. A gate region 20, which comprises a gate oxide layer 14, a polysilicon layer 16, and sidewall spacers 18, is formed on the active region of the semiconductor substrate 10. N-type (or p-type) impurity diffusion regions 22 are formed in the active region, except for the gate region 20, and the impurity diffusion regions 22 function as source and drain regions.
A barrier metal 24, such as titanium (Ti), is formed on the gate region 20 and the impurity diffusion region 22, and an interlayer-insulating layer 26, which comprises an insulating material, such as boron phosphorus silicon glass (BPSG), is formed on the Ti layer 24. Conductive plugs for electrically connecting an upper interconnection (not shown) and the Ti layer 24, for example, tungsten plugs 28, are formed to penetrate the interlayer insulating layer 26 so as to be connected with the gate region 20 and the impurity diffusion region 22.
In a conventional method of forming the barrier metal, a Ti layer is formed using a plasma enhanced chemical vapor deposition (PECVD) by dissolving TiCl4 gas using Ar and H2 plasma energy, or a TiN layer is formed using NH3 gas to secure a stable resistance. However, in a semiconductor device having a design rule of 80 nm or smaller, for example, a DRAM device, it may be difficult to ensure that capacitance characteristics are sufficiently secured and the fabrication process is stabilized with respect to a reliability of the gate oxide layer and the semiconductor device. Thus, to improve a reliability of the gate oxide layer, the fabrication may include a process of removing the defects caused in the gate oxide layer due to plasma damage incurred in a subsequent process.
FIG. 2 illustrates the process flow of a conventional method of forming barrier metal. Referring to FIG. 2, at block 100, titanium tetrachloride (TiCl4) gas is bypassed to an exhaust line to stabilize the gas, and Ar and H2 gas is supplied into a chamber having a wafer loaded therein through a gas injector part. At block 102, the TiCl4 gas is pre-flowed so as to be diffused into the chamber, and, at block 104, plasma is generated using the Ar and H2 gas supplied into the chamber. Using the Ar and H2 plasma energy generated thereby, the TiCl4 gas is dissolved to deposit Ti on the semiconductor substrate, thereby forming titanium silicide (TiSi2) on the semiconductor substrate.
At block 106, the supply of the TiCl4 gas is stopped after the silicide reaction. At block 108, a nitridation process is performed using NH3 or N2/H2 plasma to remove Cl dissolved from the TiCl4 gas during the formation process of the titanium silicide and existing in the semiconductor substrate. At block 110, the NH3 or N2/H2 plasma remaining inside the chamber is removed.
As described above, because the TiSi2 thin layer formed on the semiconductor substrate has a structure that is relatively stable at a high temperature, an ohmic contact is formed between silicon and metal so as to maintain stable resistance. The semiconductor substrate having the TiSi2 thin layer is moved to another chamber for CVD TiN in-situ, and a CVD TiN thin layer is formed using thermal energy by the chemical reaction of TiCl4 source gas and N2 gas, thereby forming a barrier metal, which comprises Ti/TiN. As such, because the barrier metal comprising Ti/TiN is formed over the active region, it may prevent a F attack from a WF6 gas during a subsequent tungsten plug formation process, thereby securing a stable contact resistance and stabilizing the characteristics of a semiconductor device.
In particular, a reliability of a gate oxide layer in a MOS transistor may have a great impact on the reliability of the entire semiconductor device. The reliability of the entire semiconductor device may be determined by the characteristics of the MOS transistor and the process conditions of backend processes of the whole fabrication of the semiconductor device. However, in the formation of the MOS transistor, the gate oxide layer may be depleted during the formation process until a contact process is performed as a backend process. As a result, leakage current characteristics may be degraded and the reliability of a MOS transistor be reduced, thereby reducing the reliability of the semiconductor device. The depletion of the gate oxide layer may be caused by defects of the silicon substrate or contamination or defects of the oxide layer, or may be caused by the dislocation of the silicon due to plasma damage or stress during a subsequent process, or contamination of the oxide layer due to contamination materials during a subsequent process.
In particular, plasma damage caused during a plasma process involved with PECVD Ti deposition may reduce the reliability of the gate oxide layer. Thus, a H2 alloy process or D2 deuterium annealing process may be performed after a metallization process has been performed in the conventional method to reduce the oxide layer failures caused by dislocation, such as mismatch of silicon crystals at the interface between the gate oxide layer and the silicon substrate. As a result of the H2 alloy process or D2 deuterium annealing process after the metallization process, silicon defects at the interface between the gate oxide layer and the silicon substrate can be somewhat removed by the passivation of H2 or D2, thereby providing an effect of increasing a reliability of the gate oxide layer. However, with the reduction of the design rule for semiconductor devices down to about 100 nm or smaller, because the area of an active region is reduced, and the area of a field region is also reduced in an STI structure, the stress applied to the silicon substrate is increased and the thickness of the gate oxide layer is reduced, thereby increasing the failures of the gate oxide layer. Particularly, because the reliability of the gate oxide layer may be significantly affected by a plasma process including PECVD Ti deposition or a metal contact etching and ashing process and the like, there is a limit to how much improvement in the reliability of the gate oxide layer may be achieved by the H2 alloy process or D2 deuterium annealing process performed after the metallization process.